The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines.
In semiconductor memory modules equipped with a plurality of very fast memory chips, for example DDR-DRAMs, arranged next to one another, there is a difficulty in precisely synchronizing the write and read data with a clock signal, said write and read data being transferred in two directions on the data bus lines between the memory chips and a memory controller device.
Therefore, in the case of previously realized semiconductor memory modules equipped with very fast memory chips, for example the latest generation of DDR-DRAMs, individual clock signal lines are routed with a precisely adjusted electrical length from the memory controller device to the individual memory chips. Another solution consists in routing two clock signal line runs on the semiconductor memory module across the memory chips arranged one after the other, the clock signals propagating in opposite directions on the two clock lines. In the case of the first solution variant therein realized in the prior art, the routing of the individual clock lines with a precisely adjusted electrical length is complicated and expensive, whereas the individual memory chips in the case of the second solution variant known in the prior art have to have separate write and read clock signal inputs.